貌似vhdl潜力可挖的地方很不少啊，_

不得不说，我对vhdl（或者说数字逻辑设计）完全是门外汉，^_^，以下两段程序：
代码片段1：
PWMcounterscreen.width/2)this.style.width=screen.width/2;>rocess(pclk, set_pwmprd_l, set_pwmhlev_l, reset_l)
   begin
      if pclkevent and pclk = 1 then
          if ((set_pwmprd_l = true_l) or (set_pwmhlev_l = true_l) or (reset_l = true_l)) then
              count_temp <= "000000000000001";
              PWM_ctrl <= 1;
          elsif (count_temp >= count_prd) then
              count_temp <= "000000000000001";
              PWM_ctrl <= 0;
          elsif (count_temp >= count_hlev) then
              count_temp <= count_temp + 1;
              PWM_ctrl <= 1;
          else
              count_temp <= count_temp + 1;
          end if;          
      end if;
   end process PWMcounter;

代码片段2：
PWMcounterscreen.width/2)this.style.width=screen.width/2;>rocess(pclk, set_pwmprd_l, set_pwmhlev_l, reset_l)
   begin
      if pclkevent and pclk = 1 then
          if ((set_pwmprd_l = true_l) or (set_pwmhlev_l = true_l) or (reset_l = true_l)) then
              count_temp <= count_prd;
              PWM_ctrl <= 0;
          elsif (count_temp <= "000000000000001") then 
              count_temp <= count_prd;
              PWM_ctrl <= 0;
          elsif (count_temp <= count_validwidth) then
              count_temp <= count_temp - 1;
              PWM_ctrl <= 1;
          else
              count_temp <= count_temp - 1;
          end if;          
      end if;
   end process PWMcounter;

这两段代码的差异仅仅在于一个是加法，另一个是减法，使用减法时，可以减少一次15bit变量的比较运算（变成了变量与常量的比较），但恰恰是这个判断，使得编译后的资源占有率从92％顿减到71％，编译时间都加快了好几倍，令我受宠若惊啊，^_^。
这段代码由于历史原因，一直使用加法，前几天想到减法可以减少一次15bit变量比较，但没有想到效果如此显著，看来以后要提高vhdl逻辑设计的水平啊，^_^